1. Field of the Invention
The present invention is related to the field of systems integrated on a semiconductor chip, and more specifically to systems having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and methods for assigning such priorities.
2. Description of the Related Art
Information computing systems, such as computer type systems, are increasingly provided on a single semiconductor chip. When they are so provided, the are called System On a Chip (SOC).
In SOC systems, various functional blocks (that are also called blocks or “IP” blocks from “Intellectual Property”) are integrated on the chip. They exchange data by a device called a bus, which is connected to all of them as a system.
Referring now to FIG. 1, an example of a typical bus system 100 is shown. Bus system 100 includes a bus 110, bus masters 120, bus slaves 160, and a bus arbiter 190. It will be observed that the functional blocks of system 100 are classified either as bus masters 120 or bus slaves 160.
Bus masters 120 need to use bus 110 to read data from or write data to one of the bus slaves 160. For such an operation, bus masters 120 need exclusive ownership of bus 110. (Bus slaves 160 cannot be granted bus ownership—they simply prepare and transmit data in response to a read or write request of a bus master 120.)
Only one master 120 can use the bus at a time. Conflicting needs between different masters 120 are resolved by bus arbiter 190. The resolution takes place as follows.
Each bus master 120 first issues a request signal REQ to bus arbiter 190, which contains a request to use bus 110 (also called ownership request). Bus arbiter 190 receives all the requests, and resolves in what order masters 120 will be granted ownership of bus 110. Then bus arbiter transmits bus grant signals GNT to the various masters 120, which contain bus grants.
Arbiter 190 resolves the order by assigning priorities to each of masters 120. Each time the bus ownership is granted to the bus master 120 having the highest priority, among those bus masters 120 issuing bus requests.
Various schemes are used for assigning priorities to bus masters, by making some decisions in advance. One such scheme is a fixed priority scheme, where the masters 120 are ranked in a fixed way. Another such scheme is a round-robin scheme, where the masters 120 receive rotating priorities depending on which one waited the longest—and once their request becomes the highest and is granted, they drop again to the bottom.
A problem specific to the SOC design is that, in addition to a system bus for the on-chip blocks, an external bus may also be used, in addition to a system bus that deals with the on-chip master blocks. An external bus is defined as a bus for accessing a read only memory (ROM), a static random access memory (SRAM), a flash memory, a dynamic RAM (DRAM), an external input/output (I/O) device and the like, which are positioned outside the chip.
This means that, for SOC design, there can be at least two buses (system bus and external bus), with respective ownerships that need to be arbitrated. This is a difficult problem, because the external devices are not part of the chip, and thus not fully known in advance.
Two main arbitration schemes have been developed for SOC designs, the exclusive arbitration scheme and the hierarchical scheme. These are described immediately below.
Referring now to FIG. 2A, a prior art system-on-a-chip 200 is shown that uses an exclusive arbitration scheme. It will be appreciated that advantages of this type of system are that the arbiter circuit is simple, and that the operational priorities of the functional blocks can be programmed.
System 200 is provided on a chip 205, which can be a semiconductor chip. System 200 includes a system bus 210 on chip 205, and an external bus 215. Each bus has its master and slave operational blocks.
Masters for the system bus 210 are the following functional blocks: a Central Processing Unit (CPU) 222, Dedicated Direct Memory Access (DDMA) blocks 224, 226, and a multi-channel General Direct Memory Access (GDMA) block 228. GDMA 228 can have four channels (e.g. numbered 0, 1, 2, and 3), that can only operate through the system bus 210 one at a time. DDMA blocks 224, 226 communicate with other IP blocks 234, 236 respectively.
Slaves for the system bus 210 are the following functional blocks: an internal memory controller 262, and an external memory controller 244. Internal memory controller 262 controls internal memory 272.
Masters for the external bus 215 are the external memory controller 244, and a Dynamic Random Access Memory (DRAM) Refresh Controller 264, that operates through controller 244. In other words, external bus 215 is subordinated to system bus 210.
Masters for the external bus 215 can also be blocks outside chip 205, which is a peculiar and different feature of the external bus. Such blocks are provided on other devices, and are also called off-chip devices. One such block can be an external device 273. External device 273 operates as an external bus master to drive the external bus 215 when it is not used by the functional blocks within the SOC chip 205, thereby effectuating a direct access to a memory 282 or external I/O devices 274 outside chip 205.
Additionally, slaves for the external bus 215 can also be off-chip blocks. In the example of FIG. 2A, slaves for bus 215 are the following functional blocks: a Read Only Memory (ROM) 282, a DRAM 284, and an external Input/Output (I/O) block 274.
System 200 includes a bus arbiter 292, which implements an exclusive arbitration scheme or method. According to the exclusive conventional bus arbitration method, each master operates as a system bus master, and only one functional block operates at any one time. The external bus is considered a slave, and external memory controller 244 serves as a hierarchical bus bridge. In this case, a selected functional block has ownership of both the system bus and the external bus. This means that the system bus and the external bus cannot be owned by different functional blocks at the same time.
In its best implementation, the exclusive arbitration scheme implemented by arbiter 292 uses a hybrid arbitration method that is described below.
Referring now to FIG. 2B, the hybrid arbitration method is described in more detail. It will be appreciated that the hybrid arbitration method is a combination of a fixed ranking scheme and a round robin arbitration scheme.
According to the hybrid arbitration method, requests 222-1, 224-1, 226-1, 228-1, 228-2, 228-3, 228-4, 264-1 are first bundled in groups according to the master blocks that originate them. Each group contains requests of equivalent importance. Request 264-1 from DRAM 264 is placed in Group A by itself. Requests 224-1, 226-1, 228-1, 228-2, 228-3, 228-4 are bundled in Group B. And request 222-1 from CPU 222 is placed in Group C by itself.
Then the groups are ranked according to their importance. Group A (request to refresh DRAM) is ranked as the most important, and Group B and Group C are bundled in a composite Group D as being equivalent.
In the example of FIG. 2B, priorities are assigned as follows. The members of Group A (i.e. requests 264-1 from DRAM 264) have a fixed priority over the members of Group D. Within Group D, there is a round robin scheme between Group B and Group C. In other words, priority alternates between the member of Group B that has the highest priority, and the member of Group C that has the highest priority (which is always a request 222-1 from the CPU 222). And within Group B, there is a round robin scheme of the members, as shown.
It should be remembered that the scheme of 2B is implemented from the point of view of arbiter 292, which is an arbiter that decides priorities between master blocks of only system bus 210.
Referring now to FIG. 2C, an example is described of the performance of system 200 of FIG. 2A. FIG. 2A shows snapshots of bus request signals REQ in association with operation of the functional blocks, and changes in the priority order of the functional blocks through eight steps of operations, labeled Step 1, Step 2, . . . , Step 8. Each step denotes a one-time operation of each functional block subjected to arbitration by bus arbiter 292. Even though steps are shown as similar, the absolute time required for executing each step may vary, depending on its nature.
For the steps of FIG. 2C, some operating assumptions have been made. These assumptions have been made only for future ease of comparison, as will be appreciated from the below.
These assumptions are first that the hybrid scheme of FIG. 2B is used. Second, that the DRAM refresh controller does not make an operation request in steps 5, 6, and 7, and that the CPU 222 makes an operation request in the step 1, while the remaining functional blocks make continuous operation requests.
As can be seen from FIG. 2C, one functional block is selected at any one time, regardless of requests for a system bus and an external bus. The selected functional block will have ownership of both the system bus and external bus. The shadowed functional block denotes one that is granted ownership to perform actual operation. However, in steps 4, 5, 6, and 7, although the selected functional block uses either only the system bus or only the external bus during its actual operation, the functional block has ownership of both buses, which degrades bus utilization.
Referring now to FIG. 3A, a prior art system-on-a-chip 300 is shown that uses a hierarchical arbitration scheme. It will be appreciated that this scheme achieves higher bus utilization over the exclusive scheme described above. This comes at a cost of having twice the number of arbiters, and that the operational priorities of all functional blocks can not be programmed as well as in the above.
System 300 is provided on a chip 305, which can be a semiconductor chip. Many components of system 300, such as the system bus 210 and functional blocks 222, 224, 234, 226, 236, 228, 244, 262, 272, and 264 are provided on chip 305, and can be identical to similarly numbered blocks in system 200, and therefore a more detailed description will not be repeated.
In addition, system-on-a-chip 300 is for connection to off-chip functional blocks 273, 274, 282, 284, similar to what was described with reference to FIG. 2A. Connection to such blocks is through an external bus 315.
Furthermore, system-on-a-chip 300 includes two arbiters 394, 396. As will be seen, progress in the prior art was made by including the second arbiter.
System bus arbiter 394 is for arbitrating requests regarding the system bus 210, and external bus arbiter 396 is for arbitrating requests regarding the external bus 315. The two arbiters 394, 396 perform what is known as hierarchical arbitration relative to each other. System bus arbiter 394 is classified as being in a higher hierarchy than external bus arbiter 396. In other words, the operation of system bus arbiter 394 is independent, while the operation of external bus arbiter 396 is a subordinate of system bus 394. (And external memory controller 244 serves as a hierarchical bus bridge.) This is illustrated below.
Referring now to FIG. 3B and FIG. 3C, these operations are illustrated. It should be noted that each one of arbiters 394, 396 requires its own separate diagram for addressing requests only of its own bus. In addition (not depicted) is the fact that requests for arbiter 396 are subordinated to requests for arbiter 394.
This achieves higher bus utilization than the exclusive arbitration scheme described above. The better utilization is illustrated by the below.
Referring now to FIG. 3D, an example is described of the performance of system 300 of FIG. 3A. It will be appreciated that FIG. 3D is analogous to FIG. 2C. In addition, the same operating assumptions have been made in FIG. 3D as for the evolution of priorities of FIG. 2C.
FIG. 3D shows snapshots of bus request signals REQ in association with operation of the functional blocks for the system bus arbiter 394 and the external bus arbiter 396. As the snapshots progress, changes are seen in the priority order of the functional blocks through eight steps of operations, labeled Step 1, Step 2, . . . , Step 8. Each step denotes a one-time operation of each functional block subjected to arbitration by bus arbiters 394, 396,
There are advantages in the hierarchical scheme. As seen in steps 6 and 7, different functional blocks having ownership of both buses can complete their operation, thereby offering higher bus utilization compared to the conventional exclusive bus arbitration scheme.
It will now be explained why the priority order of the functional blocks cannot be programmed as one wishes. As an example, in step 1 when the system bus arbiter 394 selects the CPU, the external bus arbiter 396 may intend to select GDMA channel #2. Arbiter 396 however is forced to select the CPU instead of the GDMA channel #2, since the functional block selected by the system bus arbiter 394 has a hierarchical priority over that selected by the external bus arbiter 396.
In other instances, operations are inefficient. For example, in step 2, although the system bus arbiter 394 selects DDMA block #0, the external bus arbiter 396 attempts to select the GDMA channel #2. In this case the GDMA channel #2 actually takes control of the external bus 315, since the functional block selected by the external bus arbiter 396 has a priority over that selected by the system bus arbiter 394. In this case, since the DDMA block #0 has ownership of the system bus 210, while the GDMA channel #2 has ownership of the external bus 315, the DDMA block #0 simply cannot complete its operation in the step 2. As also shown in steps 4 and 8, there are functional blocks that do not complete their operation properly during their allocated step, due to the absence of ownership of the external bus 315. When they do not, they have to wait for another step, while the external bus 315 is being used by another functional block that has ownership of the external bus 315 granted by the external bus arbiter 396.
In both of the schemes of FIG. 2A and FIG. 3A, it will be observed that there are inefficiencies. In some instances, one of the buses is occasionally idle. Such degrades the speed for the overall system on a chip.